1. Field of the Invention
The present invention generally relates to the field of semiconductor complementary metal-oxide semiconductor (hereinafter referred to as CMOS) transistor devices, and more particularly to a method of manufacturing semiconductor NMOS and PMOS transistor devices having improved saturation current (Idsat).
2. Description of the Prior Art
For decades, chip manufacturers have made transistors faster by making them smaller. FIGS. 1-5 are schematic cross-sectional diagrams illustrating a prior art method of fabricating a semiconductor CMOS transistor device. As shown in FIG. 1, an N well 12 and a P well 14 are formed in the semiconductor substrate 10. The N well 12 is isolated from P well 14 by shallow trench isolation (STI) regions 16. Polysilicon gates 18 are formed on the N well 12 and P well 14. Gate oxide layer 20 is disposed between the polysilicon gates 18 and the semiconductor substrate 10. Each polysilicon gate 18 has sidewalls 18a and a top surface 18b. 
As shown in FIG. 2, offset spacers 22 are formed on the sidewalls 18a of each polysilicon gates 18. Typically, the offset spacers 22 are silicon dioxide spacers. After the formation of the offset spacers, an ion implantation process 24 and an ion implantation process 28 are carried out to form N type lightly doped drain/source 26 and P type lightly doped drain/source 30 next to the polysilicon gates 18.
As shown in FIG. 3, silicon dioxide liner 31 and silicon nitride spacers 32 are formed on the sidewalls 18a of each polysilicon gates 18. Succeedingly, an ion implantation process 34 and an ion implantation process 38 are carried out to form N type heavily doped drain/source 36 and P type heavily doped drain/source 40 in the semiconductor substrate 10.
As shown in FIG. 4, a salicide process is carried out to form silicide layer 46 on the top surface 18b of each polysilicon gate 18, and also on the N type heavily doped drain/source 36 and P type heavily doped drain/source 40. Thereafter, a silicon nitride layer 50 having a thickness of about 300-600 angstroms is deposited over the semiconductor substrate 10. The silicon nitride layer 50 acts as a contact etch stop layer (CESL) during the etching of contact holes.
Subsequently, as shown in FIG. 5, a dielectric layer 54 is deposited on the silicon nitride layer 50. Using conventional lithographic and etching processes, contact holes are etched into the dielectric layer 54 and the silicon nitride layer 50 to expose a portion of the N type heavily doped drain/source 36 and P type heavily doped drain/source 40. Finally, the contact holes are filled with conductive plug material 60 such as tungsten. In operation, a voltage applied to the gate creates an electric field in the underlying gate channel. Depending on the polarity of the applied voltage, that field turns on or off the electric current between the transistor's source and drain.
However, the chip manufacturers have reached the point at which transistors are so small that the ability to keep shrinking them is now facing some challenges. For example, mainly because of current leakage (off-current) problem, manufacturers can no longer thin down available gate oxides as much as they used to.